SST-Core

From UFRC
Revision as of 21:24, 6 December 2019 by Moskalenko (talk | contribs) (Text replacement - "#uppercase" to "uc")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to navigation Jump to search

Description

sst-core website  

SST is an open source, cross platform simulation platform that provides a framework to connect multiple simulated hardware objects including CPUs, network, memory, etc. Simulations using the toolkit can be run either single node, or run on multiple nodes via MPI. The toolkit provides a parallel discrete event core as well as several programming interfaces including classes to manage random number generation, statistics handling, simulation output and efficient memory pooling for simulation events. The most recent performance evaluation has shown that SST can scale to simulate beyond 1.5M objects and operate efficiently on simulations up to 128 dual-processor nodes.

Required Modules

Parallel (MPI)

  • gcc/5.2.0
  • openmpi/1.10.2
  • sst-core

System Variables

  • HPC_SST-CORE_DIR - installation directory




Installation

See the SST-Core_Install page for sst-core installation notes.